Spring 2008 Instructor: Frank Hludik

Description: Design methodologies for implementing digital systems in programmable logic. Covers topics related to the design, implementation, and testing of programmable logic devices. Students are introduced to the VHDL (Very High-Speed-Hardware Description Language) design entry language and simulation procedures, along with common logic synthesis tools. Programmable logic families, device architectures, and testing procedures are covered in detail. Laboratory exercises lead the student through the complete programmable logic design cycle. Each student will prototype a digital system starting with VHDL entry, functional and timing simulations, logic synthesis, device programming, logic probing, and system verification.

Course Information:

• Course Time: MWF 14:10-15:00pm (Kingsbury W320)
• Instructor Office Hours: MWF: 15:00pm-16:00pm (W205 Kingsbury)

• TA:      Chris Rappa

Office Hours: MWF 3:00 pm to 5 :00 pm

Office: Kingsbury W214

Email: chris.rappa@unh.edu

• Syllabus

• Grading Policy:
• Design Exercises: 40%
• Homework and Quizzes: 25%
• Two Exams: 20%
• Final Comprehensive Exam: 15%

• Lecture Notes: (UNH access only)(Thanks to Frank Hludik for providing some of the materials)
• Lect 1 (01/23): Syllabus and introduction. Read Introduction to the Sun Workstations; Updates of Workstations in S324
• Lect 2 (01/28):  Reading Material (extracted from the optional book Chapter 1)
• Introduction
• Design Process
• Design Hierarchy
• Design Representation
• History of VHDL
• Lect 3: Read Tutorial on Getting Started with FPGA Advantage; Setup for HDL Designer 2003.3; Entering and Simulating a New Entity; Additional Setup
• Classification of CAD Tools
• Design Entry Tools
• Simulation - Cycle, Kernel, Efficiency
• Synthesis Tools
• VHDL Basics
• Algorithmic, Structural and Dataflow Models
• Lect 4 (02/08):
• Structural Modeling - Library and Instantiation
• Entity - Syntax
• Architecture - Syntax
• Structural Decomposition and Binding
• Component Declaration and Instantiation
• Port Mapping and Configuration
• Model Testing and Testbenches
• Block and Process
• Lect 5 (02/13):
• VHDL Lexicon
• Datatypes
• Lect 6 (02/20):
• Arrays
• Attributes 
• Midterm Review (02/25)
• Lect 8 (02/29):
• VHDL Statements
• Sequential Code
• Concurrent Code
• Lect.9
• Signal Delay
• Lect 10
• Functions
• Procedures
• Packages
• Lect 11 
• Alias
• Generic
• Signal Assignment
• Lecture 12 (3/31/08)
•     State Machines
• Lect.
• File I/O
• Textio
• Midterm II Review (04/21)
• Lect.14 (4/28/08)
• Resolved Logic
• Guards and Blocks
• Lect.15 FPGA Features

   

• Final Review (05/09)
• Problem Sets:
• HW1: Due 02/15/2008, HW1 Solution
• HW2: Due 02/22/2008, HW2 Solution
• HW3: Due 03/03/2008, Fibonacci.vhd
• HW4: Due 03/10/2008
• HW5: Due 03/24/2008 (changed to 03/26), LCD control example (ECE583 HW5!),  constraint file
• Midterm I Solution
• Laboratory Exercises:
• Laboratory Exercise I, Part I (Due 04/04/08)  Keypad Documentation
• Laboratory Exercise I, Part II (Due 04/11/08)
• Laboratory Exercise II, Part I (Due 04/23/08) Dual Port Memory Documentation
• Laboratory Exercise II, Part II - Download/Debug and Demonstrate Exercise II. Part1 (No Documentation Required) (Due 04/30/08)
• Laboratory Exercise III - Due 5/5/08
• Performing Post Place & Route Simulation
• Laboratory Exercise Four - Due 5/12/08

• Software: 
• Digilent Proto Board Documentation:
• Spartan-3E Starter Kit User Guide
• S3E_Starter_Schematic.pdf
• Xilinx Spartan 3E
• ISE Synthesis Manual
• Data Sheets
• Spartan-3E FPGA ASCII Pinouts and Excel Footprints (ZIP)
• Spartan-3 Generation FPGA User Guide
• Spartan-3 Generation Configuration User Guide (PDF)
• Application Notes:
• XAPP473 - Using the ISE Design Tools for Spartan-3 FPGAs (PDF)
• XAPP474 - Using IP Cores in Spartan-3 Generation FPGAs (PDF)
• XAPP501 - Configuration Quick Start Guidelines (PDF)
• Other Application Notes Available at Application Notes
• Precision Synthesis online tutorial (Version 2003c):
• Core Generator Tutorial
• Post Route Simulation
• Xpower: Example
• Timing Analysis: Sample Code

 

• Textbooks:
• The Designer's Guide to VHDL, 2nd edition, by P.J. Ashenden, Morgan Kaufmann (Required Purchase, Durham Book Exchange)
• VHDL Design Representation and Synthesis, Second Edition, by J. R. Armstrong and F. G. Gray, Prentice Hall PTR (Optional Purchase, Durham Book Exchange)
• VHDL Cookbook (reference)