| Date |
Topic |
Reading Assignment |
Homework/Laboratory
Assignment |
| |
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|
| 1/22 |
Course Overview |
|
|
| 1/24 |
Trends in High Speed (HS)
Design - Ch 1 |
Preface & pages 3-15 |
Exercises 1-4, 1-7, 1-8,
1-9, & 1-10 Due 1/30 |
| 1/29 |
ASIC & Backplane
Configurations - Ch 2 Introduction to Signal Integrity |
pages 17-29 Class Handout |
Exercises 2-2, 2-3, 2-5,
2-6, 2-8, & 2.9 Due 2/1 |
| 1/31 |
Signal Integrity
Temperature vs. Current
AC Resistance |
Class Handout
on Resistance
- On-Line References:
- Temperature vs.
Current
-
Temperature Charts
- Fusing Current
- Wire Gages
Read
over the Hyperlynx tutorial located on the PCs in the ECE Cluster (room
W214).
Under the start menus choose All Programs->Mentor Graphics SSD ->Hyperlynx 7.7->Hyperlynx
Tutorial. Under the Pre-layout (LineSim) heading read over the
Signal Integrity and EMC Analysis Section. This section should help
you get started with Hyperlynx modeling. |
Homework 3
Due 2/6
|
| 2/5 |
Signal Integrity Physical
Basis of Capacitance and Inductance |
Class Handout |
|
| 2/7 |
Signal Integrity Ch 3
Introduction to Transmission Line Modeling and
Characteristic Impedance |
P31 - P46 |
Laboratory Exercise 1
Due 2/15 |
| 2/12 |
Transmission Line Modeling |
|
|
| 2/14 |
Transmission Line Modeling |
|
Laboratory Exercise
II Due 2/22
|
| 2/19 |
Transmission Line Modeling
with Lattice Diagrams |
|
|
| 2/21 - 2/26 |
Transmission Line Modeling
and Termination |
|
|
| 2/28 |
Overview of EDA Tools for HS Design Design Flow for HS PCB
Design |
P571 - P623 |
Homework 4
Due 2/29
|
| 3/4 |
Cross Talk Analysis Part
1 |
- Section of Hyperlynx Tutorial on Crosstalk and
Differential Signal Analysis.
|
Laboratory Exercise III Due
3/7
|
| 3/6 |
- Cross Talk Analysis
- Part 2
|
|
|
| 3/11 |
Review for Exam I |
|
|
| 3/13 |
Exam 1 Material up to 3/11 |
|
|
| 3/25 |
Introduction to LVDS |
pages 71-104
LVDS section of on-line
documentation |
Homework 5 Problems 5-1,
5-3, 5-5, 5-8, 5-11, 5-12, 5-13, 5-14, 25-6, 25-9, and 25.11
Due 3/31
|
| 3/27 |
Differential Signal
Analysis Designing with LVDS |
pages 695- 729 |
|
| 4/1 |
Odd and Even Mode Signaling |
Class Hanndout |
|
| 4/3 |
Expedition Design Flow |
ECE Cluster |
|
| 4/8 |
BLVDS Introduction to ECL and
Associated Families
|
Chapter 6
- Chapter 8
- pages 165 - 195
|
4-3, 4-11, 6-4, 6-12, 7-1,
7-5, 7-6, 8-9, 8-16, 9-4, 9-9, and 9-10 Due 4/14 |
| 4/10 |
ECL Logic Families |
pages 165 - 195 |
|
| 4/15 |
Introduction to Current
Mode Logic |
pages 199 - 227 |
|
| 4/17 |
HSTL Families |
pages 51- 68 & 129 - 160 pages 129 - 160 |
On-Line Tutorials for Library Manager and Getting started with
Expedition
See Support Material
for Laboratory Exercises
Laboratory Exercise Four, Part
One
Due 5/1 |
| 4/22 |
No Class - ISE
Presentations |
|
|
| 4/24 |
Introduction to GTL amd
HSTL Families |
|
Laboratory Exercise
Four, Part Two
PCB Guidelines Section of
Documentation
Due 5/9 |
| 4/29 |
Introduction to IBIS Modeling |
pages 555 - 569
On-Line Reference
Material |
|
| 4/29 |
Take
Home Exam
#2 Material starting from LVDS up to,
but not including, IBIS Modeling |
|
|
| 5/1 |
Introduction to S Parameter Basics |
pages 491 - 499
On- Line
Reference Material
(top four listings) |
|
| 5/6 |
The Smith Chart and
Examples Using the Smith Chart to
Determine Input Impedance to a TL |
pages 499 - 501 |
|
| 5/8 |
S-Parameters and the Smith
Chart The Network Analyzer, TDR, and Calibration |
Class Discussion pages 501 - 516
pages 515 - 551
Understanding Network Analysis |
Network Analyzer Exercise
Hyperlynx Simulation of PCB
Design
Adding IBIS Models to Hyperlynx Due 5/12 |
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| |
DDR SDRAM DDR SDRAM
QDR SRAM |
pages 353 - 375
DDR SDRAM Material pages 375 - 389
pages 429 - 449
SRAM On-Line Material |
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