Last Updated on 03/30/2007 09:54:27 AM
by Frank Hludik

Reference Material:

Links:

Current Mode Logic (New)

• Signal Equalization I
• Signal Equalization II
• IBIS Modeling
• Interfacing CML, ECL, LVDS TI
• Interfacing CML, ECL, LVDS Maxim
• MAX3892
• NRZ Test Pattern
• Power Pad Thermal Design
• TLK2501 TI

PCB Guidelines

• Layer Stack up Guidelines
• PCB Land Pattern Guidelines
• PCB Overview
• Sample FR-4 Property Sheet
• A PCB manufacturers layer stack up example
• A PCB manufacturers layer stack up example with permittivity values

Laboratory Exercise Documentation

Expedition and IPC Material

SRAM Material

DDR SDRAM Information

S Parameter, TDR, and Smith Chart References

IBIS Information

FPGA I/O Configuration Examples

Introduction to LVDS, ECL and CML

Modeling I/O Structures

Logic Family Translation Guidelines

Mentor Graphics On-line Material

PCB Articles on Signal Integrity

Free PCB Design Calculators

UMR Trace Impedance Calculator

Electrical Engineering Calculators

EDN's Annual Microprocessor Directory

EDN's Annual Programmable Logic Directory

On-Line Documentation:

LVDS Section

• National Semiconductor LVDS Reference Manual
• FPGA I/O Configuration Examples
• Introduction to LVDS, ECL and CML
• Fail Safe Biasing
• LVDS Fundamentals
• Sample Driver Data Sheet
• Sample Receiver Data Sheet
• EMI Reduction
• PCB Guidelines for FPGA PCBs

Temperature Rise in PCB Traces

Using IPC Temperature Charts

Fusing Current

How to Gage PCB Traces

Calculation of Skin Effect

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