Home

 

Course Syllabus

 

Class Schedule

 

Tutorials

 

Assignments

 

Project

Past Projects

Links

 

 




Fall 2007

Classes, Reading Assignments and Homework/Lab Assignments

Date

Topic & Reading Assignment

Homework/Lab Assignment

Comment

1

Sept. 4

 Getting Started Course Organization

 

 

2

Sept. 6

CAD Environment (Frank Hludik), Page 1-22, Tutorial1, Tutorial2

Lab Exercise One Assigned Lab Exercise Two Assigned

 

3

Sept. 11

Lab Overview (Frank Hludik), Page 23 - 66

 

 

4

Sept. 13

Project Overview  Chapter 8. Design Methodology and Tools

Lab #1 DueLab Exercise Three Assigned,

 

5

Sept. 18

 VLSI Philosophy, Chapter 2. MOS Tarnsistor Theory, Page 67 - 108

 

 

6

Sept. 20

Review of nMOS Fundamentals

Lab #2 Due

 

7

Sept. 25

Student Project Proposal

 

 

8

Sept. 27

Review of CMOS Fundamentals

Lab #3 Due, Homework #1 Assigned

 

9

Oct. 2

Boundary scan, seminar by CJClark, Intellitech Corp

Logic Design, Chapter 6. Combinational Circuit Design, Page 319 – 378, Chapter 7. Sequential Circuit Design, Page 383 - 475

 

 

10

Oct. 4

Logic Design (Continued)

Lab #4 Due

 

11

Oct. 9

Labs and Project Review (project leaders)

Lab Exercise Four ,Assigned, Homework #1 Due

 

12

Oct. 11

 

Lab #5 Due, Homework #2 Assigned

 

13

Oct. 12

Columbus Day – no classes

 

 

14

Oct. 16

Logic Design

 

 

15

Oct. 18

Simple Layout Examples

Homework #2 Due

 

16

Oct. 23

Preliminary Design Review

Reverse Engineering Problem Assigned

 

17

Oct. 26

System Design, Chapter 10. Datapath Subsystems

Lab Exercise Five Assigned

 

18

Oct. 30

Simple Layout Examples

 

 Design Rules

19

Nov. 1

System Design

 

 

20

Nov. 6

System Design

Reverse Engineering Problem Due

 

21

Nov. 3

Floorplanning

 

 

22

Nov.13

Performance Characterization

 

 

23

Nov.15

Performance Characterization

 

 

24

Nov.20

Scaling, Page 239-266

 

 

25

Nov.22

Thanskgiving

-

-

26

Nov.27

Critical Design Review

 

 

27

Nov.30

Manufacturing

 

 

 

Dec. 4

From “Sand to Circuit” Video

 

 

28

Dec. 6

VLSI foundry Intel in Hudson MA

 Field trip

 

29

Dec. 11

Boundary Scan, Page 609 – 636 Testing and CMP

 

 

30

Dec.17

Final Design Review, Course Evaluation

 

Reading Day

 

 





 

ECE 715 Home

ECE UNH Home

 

 

 

 

This site is © Copyright University of New Hampshire 2005-2006, All Rights Reserved.

Website templates