Laboratory
Exercise 2
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Designing CMOS Circuits with Design Architect, Eldo, and IC Station Refer to the tutorials: Creating a Schematic with
Design Architect and Simulating a Design Using Eldo –
Section on Date Due: September 21, 2006 Function to Implement: _Assigned by Instructor__________________________ Purpose: 1) To become familiar with CMOS VLSI design entry and simulation at the transistor level. 2) To be able to estimate the rise times, fall times, and delays of CMOS gates, as related to the gate lengths and widths, using a SPICE based simulator. 3) To model a CMOS logic device to meet a predetermined set of timing specifications. 4) To investigate the effects of circuit variations on circuit performance. Introduction: The purpose of these laboratory exercises is to demonstrate the proper design flow for handcrafting VLSI cells. When you design your cells to meet specific criteria, i.e., speed and silicon area, first model your cells at the transistor level and use a SPICE based simulator to determine the required transistor widths and lengths (presimulation). Then enter your cells at the physical level using IC Station. After entering the devices in IC Station, extract the simulation information and resimulate (postsimulation) the cells as actually drawn. The presimulation and postsimulation results should be close to each other. If you enter your design in IC Station without presimulation information you may have a number of time consuming interactions of changing gate lengths and resimulating before you meet the desired timing parameters. Lab: Design a handcrafted CMOS
function with equally matched worst case rise and fall times. The
rise and fall times should not exceed six (6) nanoseconds with a three (3)
picofarad load on the output. Note: Two transistors in parallel have rise/fall times that are approximately one half that of a single transistor (with equal Ws and Ls), while transistors in series (with equal Ws and Ls) have rise/fall times that are double that of a single transistor. Remember the differences in the charge carrier mobilities between pMOS and nMOS transistors. Design Steps: 1) Using what you have learned from the Lab 1 enter your circuit in Design Architect using the transistors provided in analog design kit (ADK) library. Remember to add a capacitor to model the load and change its value to the one specified. Make sure you check the schematic for errors and save it. 2) Simulate the circuit in Eldo (transient analysis) to determine if it is functioning properly. Adjust the transistor widths to obtain the specified results. Remember you can easily change the widths using Eldo's change property command. Be sure to back annotate the schematic with the adjusted transistor widths. 3) Do a Hand in the: Schematic of the circuit showing correct transistor lengths and widths. Timing diagrams showing the measured rise and fall times, and delays. Note: In the next laboratory you will implement the design in IC Station and perform post simulation. |
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