Laboratory Exercise 3

 

Handcrafted Layout of a VLSI Digital Circuit In IC - STATION

 

Due 10/06/06

 

Purpose:

 

  1. Become familiar with how to represent a CMOS digital circuit at the physical level.
  2. Become familiar with the ICStation layout tool and its features.
  3. Become familiar with the relationship between physical layers and the color convention in ICStation.
  4. Become familiar with MOSIS design rules and how they determine layer spacing and minimum widths.
  5. Become familiar with using the Logic Verification Systems (LVS) to find errors in the physical layout.
  6. Learn how to back annotate the physical parasitic capacitances to your design schematic for post-simulation using ACCUSIM. 

 

Introduction:

 

      In this laboratory exercise the student will layout the design created in Laboratory Two.  Refer to Creating a Full Custom ICStation Layout for a general introduction to ICStation.  Be sure to have a copy of the design rules to use as a guide.  Try to create a layout that uses minimal silicon area. Use the technique of merging the drains to minimize the area required.

 

Note: this is your first attempt at handcrafted VLSI layout so expect that you will have to make a number of iterations before you get it correct.  Layout is a science and art; you will get better as you practice.

 

The design rule checking (DRC) features of ICStation are used to automatically check for rule violations.  LVS is used to check the layout you created in ICStation vs. your original schematic design.  Once verified with LVS, the parasitic capacitances will be back annotated to your schematic's viewpoint.  In a following laboratory exercise a post simulation will be performed to determine the effects of the extracted parasitic capacitances.

 

Procedure:

 

1.      First hand sketch your layout on paper so you have an estimate of how it will look and how the rules effect the physical locations of the layers.

2.      Open your schematic in adk_da and remove the capacitor.  Since in this exercise you will not be implementing the load capacitor, it needs to be removed to pass LVS checking.

3.      Run ICStation from the UNIX command prompt:

      adk_ic &

4.      Create a design in ICStation (refer to Laboratory Tutorial ).

  1. Enter your design and use the rule checker often to verify that what you are entering does not violate the design rules.  Some rules like pwell contact errors are reported because you have not entered them. They can be ignored in the beginning.

6.      Make sure all design rules are passed.

7.      Use LVS, as described in the Laboratory Tutorial Three, to verify that your design is entered correctly.  Correct any errors found.  See Frank Hludik for help.

 

Hand in the:

 

Schematic of the design from adk_da

Layout of the design from adk_ic

Measure and report the total area your cell occupies

The first page of the LVS report showing the layout was correct

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