Laboratory Exercise 4
Post Simulation Exercise to Determine Functionality and Actual Timing Parameters of a VLSI Full Custom Layout
Introduction:
The objective of this laboratory exercise is to lead the student through a post simulation process associated with a full-custom VLSI layout. Mach-PA timing and power analyzer
will be used to simulate the design created in exercises 2 and 3. MACH-PA is a SPICE like simulator that is used to perform pre-layout and post-layout timing simulations. This simulator is able to handle analog, digital, and mixed signal circuits. The design input to MACH-PA is a SPICE netlist, usually with extracted parasitic capacitances. A technology file describing the fabrication parameters is developed during the MACH-PA calibration process. The calibration process has been completed for the AMI05 process and the calibration file is loaded when launching the simulator. The circuit netlist is compiled into a binary file by MACH-PA. Commands to operate the simulator can be entered in the User Interface Window or placed in a command file (do file) and executed by selecting the Run Commands icon and selecting the file to run. A test vector file with input signals to force (high or low) and the desired responses (output signals) can also be created. The Run Test Vectors command applies the input signals to the circuit and checks the simulator's output signals against the desired output values in the test vector file. Errors are reported when desired outputs do not match simulated outputs.
The Mach TA simulation algorithm has three main components:
Design partitioning - Mach-PA divides the design into several partitions, allowing the simulation algorithm to evaluate only those partitions that are changing at any instant instead of evaluating the entire design. The result is high-performance without compromising accuracy.
Time-step control - Mach-PA uses a combination of time-driven and event-driven methods for time-step control.
Integration - Mach-PA employs an integration method on the linearized device models and employs non-linear convergence techniques to attain convergence. It solves the linearized models using a proprietary high-performance graph theory based matrix solution algorithm.
Procedure:
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Follow the procedures outline in the Laboratory Tutorial MENTOR GRAPHICS MACH-PA SIMULATOR. In IcStation you will create a SPICE netlist of the circuit designed in laboratory exercise two. The netlist will contain the circuit elements and extracted parasitic capacitances.
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Add a line to the netlist that instantiates a capacitor load as used in laboratory exercise 2.
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Simulate the design in MACH-PA to determine the output signal's rise and fall time and if the circuit is functioning properly. (Use the tesla workstation for MACH-PA until I can figure out why the Linux stations are crashing).
Hand in:
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Cover page with title, date and name.
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An abstract describing the full-custom design process as underwent in laboratory exercises 2, 3, and 4.
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The pre-simulation results from Eldo showing the rise and all times of the circuit designed in exercise 2.
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The print out of the IcStation layout as completed in exercise 3. State the area used to create the full-custom layout.
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Simulation results showing the correct functionality and rise/fall times from the MACH-PA timing analyzer.
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Discussion of results:
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Discussion the procedure used for a full-custom design and how this procedure helps to insure a design that meets the desired specifications.
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Discuss the relationship between the post-simulation procedure/results and pre-simulation procedure/results.
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Discuss any differences you observed between the pre- and post- simulation results and what caused these differences.
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How could the pre-simulation results be improved to better match the post-simulation results?
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What role does the Monte Carlo and step function analysis play in the design process?
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Discuss the problems that were encountered and how they were resolved.
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