Laboratory Exercise 5

 

Design a basic State Machine Using ICStation's Auto Place and Route Features

 

Introduction:

 

The objective of this laboratory exercise is to lead the student through the creation of a digital logic component using the ASIC Design Kit (ADK) library cells.  The ADK library is a family of cells that have been created and tested.  For a listing of the standard cells available for the AMI05 technology see the ADK documentation page.

 

Each ADK cell contains a symbol, transistor level circuit, physical level layout, and technology files for simulation and layout.  The logic component can be pre-simulated in Eldo for functionality, automatically placed and routed in IcStation, and post-simulated in MACH-PA.

 

This exercise will help you with the course project as it illustrates how to use the ADK cells.

 

Procedure:

 

Create a separate directory for this exercise and future designs.

For automatic place and route refer to section 4.2 in the tutorial named ADK HDL Manual.

Before invoking ICStation: run $ADK/bin/adk_dve <design> -t <tech>. This will create several viewpoints of your design. The one we will be using for automated place and route is the layout viewpoint.

Remember to set your working directory with the wd command.

 

1. Design a two bit state machine that goes through the sequence 00, 01, 10, 11, 00, etc.  The output signal "F" should be a one when the state machine is in the 11 state.  The state machine should have two inputs: clock and reset.  The state machine should have three outputs: F, qA, and qB (the two state bits).

 

2. Enter the schematic in Design Architect using the cells from the ADK Library.

 

3. Created a symbol of your state machine using the DA command Miscellaneous-> Create Symbol as described in the  Creating a Schematic tutorial.

 

4. Check and save the symbol.  Then simulate the design in Eldo as you have done in the past laboratory exercises.

 

5. Create the ADK viewpoints from the Unix command wondow:

 

adk_dve name_of_your_design -t ami05

 

7. Launch ICStation:

            adk_ic &

9. Create a new cell following the directions in section 4.2 of the ADK HDL Manual.

 

10. Using the auto-place and auto-route features of IcStation create the layout as described in section 4.2
11. Run the Short Checker as described in section 4.2
12. Use LVS as you did in a past lab to check the design to determine if it matches the schematic. ( Do not follow the procedure in section 4.3)
13. Use DRC as you did in the past to find any DRC rule violations (refer to section 4.3 in the ADK HDL Manual)
14. Use the PEX extraction as described in section 4.4. (make sure you choose the DSPF output style)
15. Prepare the netlist for MACH-TA simulation as done in laboratory exercise 4 (unh_mpa_prep design_netlist_name)
16. Start MACH-PA to confirm the circuit's functionality (start_mpa design_netlist_name.mta)
17. Create a test vector file (do file) which simplifies the process of entering input stimulus.  See Chapter 8 of the MTA User Guide
18. Use the test vector file to confirm the circuit is functioning properly
19. In MACH-PA you can calculate the power consumed by the circuit using the following two commands which first measures the RMS current from 10ns to 80 (your time values will be different) then multiplies the RMS current by 5 volts:

                 measure rms_current RMS i(vvdd) from=10ns to=810ns
                .measure power PARAM=$rms_current*5

20.     After you place, route, and simulate the design you can Add a Property to the symbol, in the Symbol Editor, allowing it to be instantiated in another cell of a hierarchical design:

             Name: phy_comp

Value: name_of_your_design

 

   Report Requirements:    

 

An abstract describing laboratory exercise 5

The schematic of your state machine

The pre-simulation results from Eldo showing the state machine working properly (show measurement of rise and fall times)

The printout of the IcStation layout

The results from the Short, LVS and DRC checks

The post-simulation results obtained from MACH-PA (show measurement of rise and fall times)

The test vector file used for MACH-PA

The power consumed by your circuit as calculated by MACH-PA

Summary of the procedures used and results obtained

 

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