COURSE CONTENT

Prerequisites by topic:

1. Boolean algebra
2. Principles of digital logic
3. Computer organization
4. Basic circuit theory and electronics
5. Ability to use a personal computer: word processing, graphics, and basic programming.

Note: ECE715 does satisfy a course requirement in the ECE Departmental Design Experience Rule.

Topics:

1. CMOS technologies
2. VLSI system design principles
3. Computer Aided Design tools (Mentor Graphics suite)
4. Technology Migration (from FPGA into ASIC)
5. Integrated circuits manufacturing
6. VLSI technologies constraints
7. VLSI testing

Course objectives and philosophy

The basic purpose of this course is to introduce senior and beginning graduate students in electrical engineering to modern microsystem design with emphasis on semi-custom and full-custom Very Large Scale Integration (VLSI). There are four fundamentals determining this process: technologies, design strategies, design tools, and implementation related limitations. The course will address all these design aspects. The specific topics will include: VLSI development tools, general design principles, system hierarchy, design styles, specific "real world" considerations such as interfacing techniques, delay, speed, power dissipation, noise, loading, etc... The course will also stress report writing, documentation, and oral communication skills. Much of the learning will occur independently in the Design Automation Laboratory (DAL). Labs will be supported by formal classroom presentations and by assistance in the lab.

Schedule for Fall and Spring Semester

During the fall semester the designs will be implemented, simulated, and submitted for fabrication. The designs will be tested and evaluated during the spring semester. A grade of course continuing (IA) will be assigned at the end of the fall semester.  A final grade will be assigned at the end of the spring semester upon completion of device testing .

There will be field trip tour to Intel's' fabrication facility in Hudson, MA.

Note: The fabricated devices should arrive back from the foundry around the first of April, 2008.

COURSE INFRASTRUCTURE  

Design content of the course

The course satisfies a design experience requirement of the Department of Electrical and Computer Engineering. The rationale behind this statement stems from the following:

The student exercises the whole prototyping sequence of a VLSI chip, from design entry, simulation, layout, post-layout simulation, submission for fabrication, verification, and testing.

Note: the ECE Department requires team-oriented projects to satisfy its design experience requirement.

VLSI project: The Design of the Computer Multicore/IP Support Repository

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&category=-1211223&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design%2BTools

Suggested Senior Project: Integration of the XILINX with the MPI Operating System Environment

BACKGROUND : TBU. 

PROJECT ORGANIZATION : The project will be coordinated by a graduate student. Each team has the following tasks to fulfil:

1.      Become familiar with boundary scan concepts;

2.      Write a description for the module you have chosen to design and implement;

3.      Create a schematic for your module using Design Architect;

4.      Simulate your design using Quicksim;

5.      Layout your design using IC station;

6.      Simulate and verify your design using the MAC timing analyzer.

7.      Prepare the database files for fabrication

8.      Test the devices when returned from the VLSI foundry

There will be periodic meetings to coordinate the effort and identify problems.

WEB usage:

An email list and help file will be used to communicate course and design information.

COURSE ORGANIZATION

 Tentative Lecture Schedule

Computer Usage:

1. Laboratory exercises that require extensive usage of computers in all stages of the development cycle (design entry, simulation, programming, testing, and verification).
2. Typed design progress reports are required.
3. Intensive testing and verification procedures are required at the development stage and the prototype evaluation stage.

Laboratory Projects (including major items of equipment and instrumentation used):

Major Equipment (available in the Design Automation Laboratory)

1. Sun/Mentor CAD workstations: SUN ULTRA Enterprise 450 server and SPARC stations
2. Functional Test Station
3. Oscilloscopes, signal generators, and logic analyzer.

Lab Schedule

Note: All lab reports have to be submitted to Frank Hludik by the due date

Design Schedule

 Grading System

Note: Ten (10) points will be deducted from an assignment's grade for each day it is late.


ABET category content is estimated by faculty member who prepared this course description:

Engineering Science: 0.5 credits or 12.5%
Engineering Design: 3.5 credits or 87.5%