| VLSI Design and Test Sequence in an Academic Environment by Pawel Nowakowski, Barbara Dziurla-Rucinska, and Andrzej Rucinski Testing is an integral part of the IC development process and its importance is steadily increasing. At the same time, there exists a shortage of test engineers in the marketplace. We observe a considerable unbalance in electrical engineering curricula between an abundance of courses offered in VLSI design/semiconductor materials and those in testing. One of the root causes is due to the cost of the course-related test equipment. This article presents an educational experience implemented at the University of New Hampshire, incorporating both the design and testing aspects in VLSI, which has been facilitated by the generous support and involvement of regional industry. Additional byproducts of the course sequence are ambitious real life projects conducted by the students. In an industrial environment, design engineers have to cooperate closely with test engineers and work together as a team for the overall good of the project and therefore the company. They have to be cross-trained to be made aware of each other's problems. The effectiveness of design and test integration is especially vital in the concurrent engineering environment, and it is really essential if time- to-market goals are to be met. However, there is still a long way to go for this real-life paradigm to be adequately reflected in engineering curricula [1]. One of the fundamental reasons for this situation can be attributed to the very high cost of the automatic test equipment. The continuing acceleration in IC technology combined with the pressure of bringing the product to market rapidly, are resulting in fundamental changes in the testing process. Electrical testing of VLSI and ULSI devices accounts for as much as 50% of total product costs [2], and these costs may escalate as the electronic devices continue to shrink. As device complexity increases, fault coverage decreases, requiring the use of design-for-test techniques, and test generation becomes a part of the design environment. This paper describes a case study of an engineering curriculum which does address both the design and testing issues in VLSI. At this stage, the design-test sequence is composed of two courses: EE715. Introduction to VLSI (a senior level course offered in the fall) and EE911, Test Engineering and Testable Design (a graduate level course, since it is still in an experimental phase) offered in the spring [3]. The first course provides a classical educational experience whereby students learn how to design, preferably in teams, VLSI chips. The designs are submitted to MOSIS in December/ January and are returned to the students for verification and test. The test experience is intended to be a follow-up senior level course. Its description is as follows: EE 911, Test Engineering and Testable Design is a graduate level course. Its goal is to introduce students to test types and methods of testing for hardware and software systems as well as to the design for testability and the strategies, planning and economics of test application. During the course students design and implement a complete production level functional test program for an IC chip. Main topics presented and discussed in class include:
There are several components of the sequence which are worth mentioning:
The lab sequence utilizes several laboratory facilities, such as the Design Automation Lab which hosts CAD tools, the Laboratory for Advanced Small Satellites [4], a provider of real life projects, and the Microelectronics Testing Laboratory. The test equipment includes a small functional tester, an industrial tester MCT2000, a wafer prober, and ECLIPSE, a boundary scan test system. The sequence is closely monitored by industrial partners: Fairchild Semiconductors Inc., and Intellitech Corporation. Fairchild Semiconductors Inc., is a co-founder of the Microelectronics Testing Laboratory, a supplier of high performance, multi-market semiconductors, and Intelltech Corp. is a provider of scan-based tools. A close relationship with industrial partners gives students and faculty direct contact with industry, resulting in access to tools and technology, and real life projects. This year we have conducted the following projects in the test course:
There are five laboratory experiments in the VLSI course and four laboratory experiments in the testing course. The first assignment in testing, preceded by lab demonstration and in-class presentations, aims at familiarizing students with the test tools used at the Microelectronics Testing Laboratory – MTC2000 hardware and software environments. In the first assignment, students have to comment on example test procedures, analyze applied test vectors, and answer questions related to the tester architecture. To accomplish these tasks students use tutorials and reference manuals available on the web and information presented in class by a lab assistant and test engineers. The main goal of test experiments is to have students become familiar with the overall process of test program development. All students are assigned simple IC devices for which they develop test procedures. To implement their tests students modify previously prepared test program templates such as ones for a simple 74F00 bipolar two-input NAND gate. Students are guided through a lab experiment, which shows a test suite for the NAND logic package as illustrated below.
By the end of the course students design and implement complete test programs for their devices. We recognized the importance of the Internet in education quite a long time ago [6]. Therefore, the course-related information is available via web browsers. It includes the course description, laboratory descriptions, contact information, assignments and solutions, formation of teams and their projects, tutorials, auxiliary teaching materials, and links to related sites [7]. During the course sequence students learned first hand that VLSI testing is a collaborative effort between electrical engineers and test program developers. In the course we have students testing both their own chips (designed by themselves) and someone else's chips. In the first case, the designer and the test developer do not need to communicate, which results in faster development of test procedures. In the second case the testing person is more "objective" about the task and provides a different viewpoint about testing. Our future plans include the introduction of the described course at the senior level as well as the introduction of a new graduate course in testing with emphasis on advanced research topics such as system level testing and boundary scan. The authors want to acknowledge and thank Gerry Fortin, Fairchild Semiconductors Inc., and C.J. Clark, Intellitech Corporation, for their support and involvement in building up the test program at the University of New Hampshire. [1] http://microsys6.engr.utk.edu/~bouldin [2] Eugene R. Hnatek, Integrated Circuit Quality and Reliability, Marcel Dekker, 1995. [3] http://www.ece.unh.edu [4] http://www.catsat.sr.unh.edu [5] K. Parker, The Boundary Scan Handbook, Kluwer Academic Publisher, Boston, 1998 [6] B. Dziurla-Rucinska and A. Rucinski, "Cyberspatial university", IEEE Potentials, August/September 1996 [7] http://www.ece.unh.edu/courses/EE911/index.html |