The Fairchild/UNH development team. From left to right are Jean Boisvert, Tamas Visegrady, Pawel Nowakowski, Mark Caradonna, Ryan Walsh, Aaron Howard, Joseph Stocker, Daren Keller, Frank Hludik, Barbara Rucinska, Andrzej Rucinski, and Gerry Fortin.

The Fairchild Pin-Card Upgrade Project

by Frank Hludik

In last summer’s issue of Signals and Noise we reported the establishment of the Fairchild/UNH Microelectronics Testing Laboratory. During the past year the laboratory has been a busy place. The students working on the MCT2000 (microelectronics tester) pin-card upgrade project used the laboratory to test the hardware and software they developed over the past year. Professor Rucinska’s graduate level testing course (EE911 - Test Engineering and Testable Design) used the laboratory to conduct testing exercises throughout the spring semester.

This article describes the process of designing the pin card upgrade for the MCT2000 tester. The goal of the project was to upgrade the MCT2000 from a 64 pin tester to a 256 pin tester. The testing capabilities and speed of the tester were to remain the same, with some enhancements. Since testers require high-speed logic with predictable delays, most use emitter coupled logic (ECL) to deliver test vectors and capture responses from a device under test (DUT). Meeting the power and thermal requirements was a challenge, since the logic was increased by a factor of four. A combination of CMOS field programmable gate arrays (FPGAs) and ECL logic was selected to keep the power and thermal properties to a minimum.

Testers for digital devices are usually comprised of two major systems, one dynamic and the other steady state. The dynamic system verifies functionality, timing parameters, and input/output voltage parameters under actual operating conditions (functional testing), while the other system measures the steady state conditions of all input/output pins under different load and power supply conditions (DC parameter testing). The dynamic system was to be updated by UNH to allow higher pin count devices to be tested on the MCT2000. The current MCT2000 tester had one PCB pin card for each pin being tested on a DUT. UNH’s task was to understand the current MCT2000’s functional testing system and then design a pin card that would be capable of testing four pins on a DUT, increasing the capabilities by a factor of four.

It is important for a VLSI manufacturer, and the consumer, to be confident that the devices they are manufacturing are meeting their specified parameters. Each device manufactured must undergo rigorous testing to verify its functionality and DC parameters. The testing process must not only be precise and cost effective, but must also help the manufacturer quickly determine the source of problems in the wafer manufacturing process. It became evident from the beginning of this project that redesigning the MCT2000 pin card was no small task. It would be a challenge for all parties involved.

The MCT2000 pin card upgrade had eight subsections:

The functional sequencer interface, which consists of static memory that stores the test vectors and a high speed CMOS FPGA that formats the test vectors into patterns that can be delivered to the pin driver circuit.

The high-speed ECL pin driver circuit that delivers the test pattern to a DUT’s input pin. This circuit has adjustable high and low voltage output levels.

The ECL comparator subsection that captures the state of an output pin and determines if it is a logic high, low, or tri-state according to settable values.

The high-speed ECL circuit that verifies that the output response of a pin is correct. This interfaces to a high-speed CMOS FPGA that formats the desired response from the applied test pattern. It also informs the MCT2000 bus of an error condition.

The programmable load circuit that when applied to the output pin of a DUT matches actual load conditions.

DAC and amplifier subsections that set voltage levels that determine the output levels of the pin driver circuits, high and low logic levels of the comparator circuits, and load conditions (current and switching levels) of the programmable load circuits.

High pin count (208 pins) CMOS FPGA that controls the interface between the MCT2000 bus and pin card programmable subsections.

ECL programmable delay circuits that match the delays on pin driver and comparator channels.

One of the first steps in any project is to assemble the design team. As in any university environment, this means recruiting students from the graduate and undergraduate classes. Tamas Visegrady and Pawel Nowakowski, both graduate students at UNH, joined the team from the outset. Tamas, who received his doctorate from UNH in May 1999, led the hardware development while Pawel, a computer science major, developed the algorithms that were used to test the hardware during the development cycle. Four undergraduates (Mark Caradonna, Ryan Walsh, Aaron Howard, and Joseph Stocker) joined the team while in their junior year at UNH. All four graduated in May 1999. Daren Keller, an ECE junior, worked part time during last winter and spring.

Next comes determining the design requirements, attempting a schedule, and in any upgrade project, reverse engineering the product one is upgrading. Establishing design requirements requires extremely good communication, both at the technical and conceptual levels. (This is a plug for developing one's communication skills.) Fortunately for us, Fairchild Corporation assigned a very knowledgeable team of engineers to work with us throughout the project. The scenario is: study documentation, discuss requirements, and ask questions (until everything is completely understood). If one is too shy to ask questions, for whatever reason, one will find himself in trouble.

In a university environment the "progress clock" ticks at many paces. During summers and winter breaks the clock moves at a normal pace, during the beginning of the semester it slows down, and usually comes to a grinding halt as the semester reaches its ending climax. Scheduling events (time line) such as task assignments and design reviews is a challenge. The rule of thumb is "it always takes twice as long as you think." Those unforeseen events just never seem to go away. A time line is very valuable as it helps to put the entire project in perspective and keeps track of actual progress.

Since we had to interface the UNH pin card design with the existing MCT2000 system, understanding the tester and the testing process was a must. Reverse engineering, the next step in our design process, required putting oneself in the shoes of the original designers of the MCT2000. What does the system do? How did they make it work? Does the documentation match actual performance? It quickly become evident that documentation is extremely important.

After the design team had a working knowledge of how the MCT2000 functioned, the design process began. Preliminary top-level subsystems were designed and parts selected. Conferences between Fairchild and UNH confirmed that we were on the right track or needed to modify our preliminary designs. After a number of Fairchild/UNH preliminary design reviews the students entered the entire design in our Mentor Graphics CAD system. The undergraduate students divided responsibilities into system design, FPGA subsystems, and ECL subsystems. As one may know from experience, the ideal design and reality are not always identical. Parts don’t always perform as advertised, documentation doesn’t always give enough information to understand the functionality of a part, and the physical layout of parts and routing can play a major factor in performance. It was evident that individual subsystems had to be prototyped and tested before the final printed circuit board (PCB) design of the pin card could be placed, routed, and fabricated.

The ECL high-speed sections required prototyping using PCB technology. Therefore, we decided to get into the in-house PCB manufacturing business allowing us to fabricate a PCB within a few days. Equipment was purchased and after a few tries the students were able to fabricate two-sided PCBs with 0.010" pitch traces and ground planes. Since the majority of the system was going to be prototyped, subsystems were designed so they could be interconnected and assembled together. As we anticipated, assembling the individual prototypes into a system was a challenge. We were able to confirm functionality, allowing the final system PCB design to progress. After a number of PCB part layout attempts and final approval from the Fairchild team, the PCB was sent out for fabrication. The layout and routing challenges were to place the parts according to their thermal properties, properly terminate the traces, match the traces on pin-driving circuits for equal delays, minimize delays on driving and capture circuits, and keep cross talk to acceptable levels. Our first system PCB was somewhat of a success. Murphy’s law kicked in and there were a few missing power connections and shorted power lines.

In the true spirit of team work fingers were never pointed. We had a challenging design to complete, more challenging than we had originally anticipated, and the clock was ticking. We were able to jumper missing traces and cut shorted traces. The first PCB design was functional enough to allow us to continue with system level testing. A second PCB was redesigned with corrections and fabricated.

Industrial projects like this one provide students with essential experience. Not only do they have the opportunity to apply what they have learned in the classroom and laboratories, but they are exposed to many facets of engineering that simply can’t   be learned in the classroom. For example, seeing how an ECL high-speed circuit performs with a poor solder joint or improper line termination is a lesson in itself. A good design engineer must be well versed in all levels of a project from system level concepts, to design entry, simulation, prototyping, assembly, testing, and documentation. Students learn that team interactions are vital and how a team functions can either make a project successful or lead to the failure of a project.

We are grateful to Fairchild Corporation in South Portland, Maine for giving us the opportunity to work with them on this project. A good working relationship was established from the management to engineering levels. Our special thanks go to Gerry Fortin Director of Device Engineering and Worldwide Wafer Sort at Fairchild Corporation in South Portland, who spearheaded the project; Ray Roberts a Fairchild hardware engineer who knew every aspect of the MCT2000 tester; and Jean Boisvert who wrote the operating environment for the MCT2000.