Mixed Signal Boundary Scan: A Solution for testable VSLI Design

by Andrzej Rucinski

An accelerated convergence of different trends that are transforming engineering education into a more coherent but highly heterogeneous system has been observed for quite some time. Education in microelectronics is relatively novel, but is still a consistent addition to this phenomenon. An introduction of SOCs, IP, and MEMs promotes multidisciplinary and team oriented education. Team oriented experience is also mandated by ABET [1] and recognized by faculty involved in microelectronics. Traditionally, multidisciplinary curricula focus on physically large system development such as satellite design [2]. However, the same challenges that face system developers exist in microelectronics education despite better defined design specifications and simplified logistics.

As a case study, a VLSI implementation of an IEEE 1149.4 compatible device was selected. The standard specifies design requirements for mixed signal microelectronic devices using the principles of boundary scan. Boundary scan enhances the observability and controllability of a device, thus making it more testable. The design, patterned after a MNABST-1 chip, satisfies several educational objectives such as: (i) the groundwork for SOC design; (ii) development of a reusable boundary scan library; (iii) emphasis on test and testability [4]; (iv) The device, shown above, has been developed using the AMI 0.5 micron CMOS technology, using Mentor Graphics CAD tools, the ADK cell-based library, and the MOSIS 40-pin DIP ceramic package.

Students were divided into three design teams: VHDL Team of six students; Cell-Based Team I of five students; and Cell-Based Team II of six students. All designs were functionally equivalent, with identical pin-out scheme. Any core logic compliant with pin and silicon estate requirements was permitted. Within each team, two person subsystem teams were formed targeting IEEE 1149.4 modules: TAP with glue logic, ABM, and TBIC [3] respectively. A special integrating and management task was assigned to the student project leader, Kristina Pisareva, supported by teaching assistant Roman Kozakowski. The test phase was conducted by all of the students, however a designated team of students was responsible for the development of test vectors and domestication of two ATE testers: MCT2000 (traditional) and Eclipse (boundary scan) A picture below shows some of the students involved in the project.

Some of the Students Involved in the Project

In summary, this useful experience exhibited the multiplicity of difficult challenges facing management involved in system design. They were not easy to overcome despite a well- specified design conducted by the students with almost identical engineering backgrounds. The design process was not routine, and the learning curve was further complicated by the introduction of several new components such as new technology and CAD tools. However, the technical aspects and search for new solutions did not appear to impede the design progress. Clearly, the excellence of education in microelectronic systems design is determined by the quality of management and organization, which become the dominant factors. Currently, we are in the process of refining the VLSI designs. They will be resubmitted for fabrication this summer and next fall as part of another VLSI course.

It has to be mentioned that our effort would not be possible without extensive support from companies such as Fairchild Semiconductors Inc, Intellitech Corporation, National Semiconductor and organizations such as NSF and MOSIS. Kristina Pisareva presented her work at the ATW Workshop in Corsica, France this July.

References

[1] J.Yeargan, "The effect of ABET’s EC2000 on curriculum: early indications", Proc. 1999 Int. Conf. on Microelectronic Systems Education MSE’1999, Arlington, VA, July 1999.

[2] A.Rucinski, D.Forrest, and B.Rucinska, "Curriculum in engineering team management with strong scientific and high-tech design components", Proc. 3^rd East-West Congress on Engineering Education, Gdynia, Poland, September 1996.

[3] K.Parker, The boundary scan handbook, Kluwer Academic Publisher, Boston, 1998.

[4] P.Nowakowski, B.Rucinska, and A.Rucinski, "VLSI design and test sequence in an academic environment: a case study", Proc. Int. Conf. on Microelectronic Systems Education MSE’1999, Arlington, VA, July 1999.